//////////////////////////////////////////////////////////////////////////////
// Inverter
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORInverter
// An inverter with sizing parameters and parameterized AD,AS,PD,PS
// The S/D parameters assume a single-finger device
// Also has parameterized scaling for logical effort
subckt TeamXORInverter VDD VSS in out 
parameters wp=2.33u wn=1.5u ln=600n lp=600n mult=1 alpha=1
    MP (out in VDD VDD) ami06P w=wp*alpha l=lp as=1.5u*wp*alpha ad=1.5u*wp*alpha ps=3u+wp*alpha pd=3u+wp*alpha m=mult
    MN (out in VSS VSS) ami06N w=wn*alpha l=ln as=1.5u*wn*alpha ad=1.5u*wn*alpha ps=3u+wn*alpha pd=3u+wn*alpha m=mult
ends TeamXORInverter
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// Buffer Stage (2 inverters in series)
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORBuffer
// A buffer stage which instantiates two inverters in series.
// Easier instantiating buffers in simulation.
subckt TeamXORBuffer VDD VSS in outBuff
parameters wp0=2.33u wn0=1.5u lp0=600n ln0=600n alphafirst=1 multfirst=1 alphasecond=1 multsecond=1
    IB0 (VDD VSS in inbar) TeamXORInverter wp=wp0 wn=wn0 lp=lp0 ln=ln0 alpha=alphafirst mult=multfirst
    IB1 (VDD VSS inbar outBuff) TeamXORInverter wp=wp0 wn=wn0 lp=lp0 ln=ln0 alpha=alphasecond mult=multsecond
ends TeamXORBuffer
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 2input NAND
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2inNAND
subckt TeamXOR2inNAND VDD VSS inA inB out
parameters wp=2.33u wn=1.5u ln=600n lp=600n mult=1
    P0 (out inB VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
    P1 (out inA VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
    N0 (out inA nAB VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
    N1 (nAB inB VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
ends TeamXOR2inNAND
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 3input NAND
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR3inNAND
subckt TeamXOR3inNAND VDD VSS inA inB inC out
parameters wp=2.33u wn=1.5u ln=600n lp=600n mult=1
    P0 (out inC VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
    P1 (out inB VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
    P2 (out inA VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
    N0 (out inA nAB VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn m=mult
    N1 (nAB inB VBC VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn m=mult
    N2 (nBC inC VSS VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn m=mult
    ends TeamXOR3inNAND
// End of subcircuit definition.




//////////////////////////////////////////////////////////////////////////////
// 2 input AND
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2inAND
subckt TeamXOR2inAND VDD VSS inA inB out
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n mult1=1
    I0 (VDD VSS inA inB outNAND) TeamXOR2inNAND wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
    I1 (VDD VSS outNAND out) TeamXORInverter wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
    ends TeamXOR2inAND
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 16 bit, 2 input AND
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR16b2inAND
subckt TeamXOR16b2inAND VDD VSS inA15 inA14 inA13 inA12 inA11 inA10 inA9 inA8 inA7 inA6 inA5 inA4 inA3 inA2 inA1 inA0 \
    inB15 inB14 inB13 inB12 inB11 inB10 inB9 inB8 inB7 inB6 inB5 inB4 inB3 inB2 inB1 inB0 outAB15 outAB14 outAB13 \
    outAB12 outAB11 outAB10 outAB9 outAB8 outAB7 outAB6 outAB5 outAB4 outAB3 outAB2 outAB1 outAB0
parameters wp2=2.33u wn2=1.5u ln2=600n lp2=600n mult2=1
    IT15 (VDD VSS inA15 inB15 outAB15) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT14 (VDD VSS inA14 inB14 outAB14) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT13 (VDD VSS inA13 inB13 outAB13) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT12 (VDD VSS inA12 inB12 outAB12) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT11 (VDD VSS inA11 inB11 outAB11) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT10 (VDD VSS inA10 inB10 outAB10) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT9 (VDD VSS inA9 inB9 outAB9) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT8 (VDD VSS inA8 inB8 outAB8) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT7 (VDD VSS inA7 inB7 outAB7) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT6 (VDD VSS inA6 inB6 outAB6) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT5 (VDD VSS inA5 inB5 outAB5) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT4 (VDD VSS inA4 inB4 outAB4) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT3 (VDD VSS inA3 inB3 outAB3) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT2 (VDD VSS inA2 inB2 outAB2) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT1 (VDD VSS inA1 inB1 outAB1) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT0 (VDD VSS inA0 inB0 outAB0) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
ends TeamXOR16b2inAND
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 2 input NOR
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2inNOR
subckt TeamXOR2inNOR VDD VSS inA inB out
parameters wp=2.33u wn=1.5u ln=600n lp=600n mult=1
    P1 (pAB inA VDD VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp m=mult
    P0 (out inB pAB VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp m=mult
    N0 (out inA VSS VSS) ami06N w=wn l=lp1 as=1.5u*wn ad=1.5u*wn ps=3u+wn pd=3u+wn m=mult
    N1 (out inB VSS VSS) ami06N w=wn l=lp1 as=1.5u*wn ad=1.5u*wn ps=3u+wn pd=3u+wn m=mult
ends TeamXOR2inNOR
//Ends subckt definition.



//////////////////////////////////////////////////////////////////////////////
// 2 input OR
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2inOR
subckt TeamXOR2inOR VDD VSS inA inB out
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n mult1=1
    I0 (VDD VSS inA inB outNAND) TeamXOR2inNOR wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
    I1 (VDD VSS outNAND out) TeamXORInverter wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
ends TeamXOR2inOR
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 16 bit, 2 input OR
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR16b2inOR
subckt TeamXOR16b2inOR VDD VSS inA15 inA14 inA13 inA12 inA11 inA10 inA9 inA8 inA7 inA6 inA5 inA4 inA3 inA2 inA1 inA0 \
    inB15 inB14 inB13 inB12 inB11 inB10 inB9 inB8 inB7 inB6 inB5 inB4 inB3 inB2 inB1 inB0 outAB15 outAB14 outAB13 \
    outAB12 outAB11 outAB10 outAB9 outAB8 outAB7 outAB6 outAB5 outAB4 outAB3 outAB2 outAB1 outAB0
parameters wp2=2.33u wn2=1.5u ln2=600n lp2=600n mult2=1
    IT15 (VDD VSS inA15 inB15 outAB15) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT14 (VDD VSS inA14 inB14 outAB14) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT13 (VDD VSS inA13 inB13 outAB13) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT12 (VDD VSS inA12 inB12 outAB12) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT11 (VDD VSS inA11 inB11 outAB11) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT10 (VDD VSS inA10 inB10 outAB10) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT9 (VDD VSS inA9 inB9 outAB9) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT8 (VDD VSS inA8 inB8 outAB8) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT7 (VDD VSS inA7 inB7 outAB7) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT6 (VDD VSS inA6 inB6 outAB6) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT5 (VDD VSS inA5 inB5 outAB5) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT4 (VDD VSS inA4 inB4 outAB4) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT3 (VDD VSS inA3 inB3 outAB3) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT2 (VDD VSS inA2 inB2 outAB2) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT1 (VDD VSS inA1 inB1 outAB1) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    IT0 (VDD VSS inA0 inB0 outAB0) TeamXOR2inOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
ends TeamXOR16b2inOR
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 2 to 4 Decoder for Shifter
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2to4Decoder
// Decodes the 2 LSB of B to determine how many bits to shift A 
subckt TeamXOR2to4Decoder VDD VSS inB1 inB0 outSL1 outSL2 outSL3 outSL4
parameters wp2=2.33u wn2=1.5u ln2=600n lp2=600n mult2=1
    I10 (VDD VSS inB1 inB1bar) TeamXORInverter wp=wp2 wn=wn2 ln=ln2 lp=lp2 mult=mult2
    I8 (VDD VSS inB0 inB0bar) TeamXORInverter wp=wp2 wn=wn2 ln=ln2 lp=lp2 mult=mult2
    I7 (VDD VSS inB1bar inB0bar outSL1) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    I4 (VDD VSS inB1 inB0 outSL4) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    I5 (VDD VSS inB1 inB0bar outSL3) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
    I6 (VDD VSS inB1bar inB0 outSL2) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
ends TeamXOR2to4Decoder
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 16 bit Shifter without Decoder of 2 LSB of B
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR16bShifter
subckt TeamXOR16bShifter VDD VSS NOP Left1 Left2 Left3 Left4 inA15 inA14 inA13 inA12 \
    inA11 inA10 inA9 inA8 inA7 inA6 inA5 inA4 inA3 inA2 inA1 inA0 outA15 outA14 outA13 outA12 outA11 \
    outA10 outA9 outA8 outA7 outA6 outA5 outA4 outA3 outA2 outA1 outA0
parameters wp3=2.33u wn3=1.5u ln3=600n lp3=600n mult3=1 alphafirst0=1 alphasecond0=1
    B0 (VDD VSS preoutA0 outA0) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B1 (VDD VSS preoutA1 outA1) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0

    B2 (VDD VSS preoutA2 outA2) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B3 (VDD VSS preoutA3 outA3) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B4 (VDD VSS preoutA4 outA4) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0    
    
    B5 (VDD VSS preoutA5 outA5) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B6 (VDD VSS preoutA6 outA6) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0

    B7 (VDD VSS preoutA7 outA7) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B8 (VDD VSS preoutA8 outA8) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0

    B9 (VDD VSS preoutA9 outA9) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B10 (VDD VSS preoutA10 outA10) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B11 (VDD VSS preoutA11 outA11) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B12 (VDD VSS preoutA12 outA12) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B13 (VDD VSS preoutA13 outA13) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B14 (VDD VSS preoutA14 outA14) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
    B15 (VDD VSS preoutA15 outA15) TeamXORBuffer wp0=wp3 wn0=wn3 ln0=ln3 lp0=lp3 alphafirst=alphafirst0 alphasecond=alphasecond0
    
     
    N93 (preOutA0 Left1 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N95 (preOutA0 Left3 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N96 (preOutA0 Left4 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N98 (preOutA1 Left4 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N97 (preOutA2 Left3 VSS VSS)  ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N100 (preOutA1 Left2 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N102 (preOutA3 Left4 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N103 (preOutA2 Left4 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N89 (preOutA12 Left4 inA8 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N90 (preOutA13 Left4 inA9 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N91 (preOutA14 Left4 inA10 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N92 (preOutA15 Left4 inA11 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N88 (preOutA11 Left4 inA7 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N77 (preOutA12 Left3 inA9 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N82 (preOutA5 Left4 inA1 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N78 (preOutA13 Left3 inA10 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N75 (preOutA10 Left3 inA7 VSS)ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N76 (preOutA11 Left3 inA8 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N83 (preOutA6 Left4 inA2 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N86 (preOutA9 Left4 inA5 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N79 (preOutA14 Left3 inA11 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N87 (preOutA10 Left4 inA6 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N80 (preOutA15 Left3 inA12 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N84 (preOutA7 Left4 inA3 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N74 (preOutA9 Left3 inA6 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N70 (preOutA5 Left3 inA2 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N71 (preOutA6 Left3 inA3 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N72 (preOutA7 Left3 inA4 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N73 (preOutA8 Left3 inA5 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N85 (preOutA8 Left4 inA4 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N81 (preOutA4 Left4 inA0 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N68 (preOutA3 Left3 inA0 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N69 (preOutA4 Left3 inA1 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N99 (preOutA1 Left3 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N54 (preOutA15 Left2 inA13 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N55 (preOutA14 Left2 inA12 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N56 (preOutA13 Left2 inA11 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N57 (preOutA12 Left2 inA10 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N58 (preOutA11 Left2 inA9 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N59 (preOutA10 Left2 inA8 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N60 (preOutA6 Left2 inA4 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N61 (preOutA7 Left2 inA5 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N62 (preOutA8 Left2 inA6 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N63 (preOutA9 Left2 inA7 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N64 (preOutA5 Left2 inA3 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N65 (preOutA4 Left2 inA2 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N52 (preOutA4 Left1 inA3 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N51 (preOutA3 Left1 inA2 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N50 (preOutA2 Left1 inA1 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N49 (preOutA1 Left1 inA0 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N48 (preOutA5 Left1 inA4 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N47 (preOutA6 Left1 inA5 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N46 (preOutA7 Left1 inA6 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N45 (preOutA8 Left1 inA7 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N44 (preOutA12 Left1 inA11 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N43 (preOutA11 Left1 inA10 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N42 (preOutA10 Left1 inA9 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N41 (preOutA9 Left1 inA8 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N40 (preOutA13 Left1 inA12 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N39 (preOutA14 Left1 inA13 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N38 (preOutA15 Left1 inA14 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N36 (preOutA3 NOP inA3 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N35 (preOutA2 NOP inA2 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N34 (preOutA1 NOP inA1 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N33 (preOutA0 NOP inA0 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N94 (preOutA0 Left2 VSS VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N28 (preOutA11 NOP inA11 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N27 (preOutA10 NOP inA10 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N26 (preOutA9 NOP inA9 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N25 (preOutA8 NOP inA8 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N66 (preOutA3 Left2 inA1 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N31 (preOutA5 NOP inA5 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N30 (preOutA6 NOP inA6 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N32 (preOutA4 NOP inA4 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N29 (preOutA7 NOP inA7 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N4 (preOutA12 NOP inA12 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N2 (preOutA14 NOP inA14 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N1 (preOutA15 NOP inA15 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N67 (preOutA2 Left2 inA0 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    N3 (preOutA13 NOP inA13 VSS) ami06N w=wn3 l=ln3 as=1.5u*wn3 ad=1.5u*wn3 ps=3u+wn3 pd=3u+wn3 m=mult3
    
ends TeamXOR16bShifter
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 16 bit Shifter with Decoder of 2 LSB of B
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORFinal16bShifter
subckt TeamXORFinal16bShifter VDD VSS inB1 inB0 inA15 inA14 inA13 inA12 inA11 inA10 inA9 inA8 inA7 inA6 inA5 inA4 inA3 inA2 inA1 inA0 \
    outA15 outA14 outA13 outA12 outA11 outA10 outA9 outA8 outA7 outA6 outA5 outA4 outA3 outA2 outA1 outA0
parameters wp4=2.33u wn4=1.5u ln4=600n lp4=600n mult4=1
    I1 (VDD VSS inB1 inB0 wireSL1 wireSL2 wireSL3 wireSL4) TeamXOR2to4Decoder wp2=wp4 wn2=wn4 ln2=ln4 lp2=lp4 mult2=mult4
    I0 (VDD VSS 0 wireSL1 wireSL2 wireSL3 wireSL4 inA15 inA14 inA13 inA12 inA11 inA10 inA9 inA8 inA7 inA6 inA5 inA4 inA3 \
    inA2 inA1 inA0 outA15 outA14 outA13 outA12 outA11 outA10 outA9 outA8 outA7 outA6 outA5 outA4 outA3 outA2 outA1 outA0) \
    TeamXOR16bShifter wp3=wp4 wn3=wn4 ln3=ln4 lp3=lp4 mult3=mult4
ends TeamXORFinal16bShifter
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 2 input XOR
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2inXOR
// A 2-input XOR gate using all NANDs
subckt TeamXOR2inXOR VDD VSS inA inB out
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n mult1=1
   LeftNAND (VDD VSS inA inB net10) TeamXOR2inNAND wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
   BottomNAND (VDD VSS net10 inB net15) TeamXOR2inNAND wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
   RightNAND (VDD VSS net25 net15 out) TeamXOR2inNAND wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
   TopNAND (VDD VSS inA net10 net25) TeamXOR2inNAND wp=wp1 wn=wn1 ln=ln1 lp=lp1 mult=mult1
ends TeamXOR2inXOR
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// Half Adder
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORHalfAdder
// Half adder circuit for use in tree multiplication.
subckt TeamXORHalfAdder VDD VSS A B S Cout                                                                          
parameters wp2=2.33u wn2=1.5u ln2=600n lp2=600n mult2=1
   I0 (VDD VSS A B S) TeamXOR2inXOR wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
   I1 (VDD VSS A B Cout) TeamXOR2inAND wp1=wp2 wn1=wn2 ln1=ln2 lp1=lp2 mult1=mult2
ends TeamXORHalfAdder
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// Transmission Gate (TXGate)
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORTXGate
subckt TeamXORTXGate VDD VSS N P In Out
parameters wp=2.33u wn=1.5u ln=600n lp=600n mult=1 alpha=1
    P0 (Out P In VDD) ami06P w=wp*alpha l=lp as=1.5u*wp*alpha ad=1.5u*wp*alpha ps=3u+wp*alpha pd=3u+wp*alpha m=mult 
    N0 (In N Out VSS) ami06N w=wn*alpha l=ln as=1.5u*wn*alpha ad=1.5u*wn*alpha ps=3u+wn*alpha pd=3u+wn*alpha m=mult
ends TeamXORTXGate
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 2 to 1 MUX
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR2to1MUX
subckt TeamXOR2to1MUX VDD VSS in0 in1 Select Out
parameters wp0=2.33u wn0=1.5u ln0=600n lp0=600n mult0=1 alpha0=1
    TXGateTop (VDD VSS Selectbar Select in0 Out) TeamXORTXGate wp=wp0 wn=wn0 ln=ln0 lp=lp0 mult=mult0 alpha=alpha0
    TXGateBottom (VDD VSS Select Selectbar in1 Out) TeamXORTXGate wp=wp0 wn=wn0 ln=ln0 lp=lp0 mult=mult0 alpha=alpha0
    I6 (VDD VSS Select Selectbar) TeamXORInverter wp=wp0 wn=wn0 alpha=alpha0
ends TeamXOR2to1MUX
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// Positive Level Sensitive Latch
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORPositiveLatch
subckt TeamXORPositiveLatch VDD VSS CLK D Qfinal
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n mult1=1
    MUX0 (VDD VSS Qfinal D CLK Qint) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1
    B0 (VDD VSS Qint Qfinal) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1   
ends TeamXORPositiveLatch
// End of subcircuit definition.


//////////////////////////////////////////////////////////////////////////////
// Negative Level Sensistive Latch
//////////////////////////////////////////////////////////////////////////////

//// Cell name: TeamXORNegativeLatch
subckt TeamXORNegativeLatch VDD VSS CLK D Qfinal
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n mult1=1
    MUX0 (VDD VSS D Qfinal CLK Qint) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1
    B0 (VDD VSS Qint Qfinal) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1   
ends TeamXORNegativeLatch
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// Positive Edge Triggered Register
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORPositiveEdgeTriggeredRegister
subckt TeamXORPositiveEdgeTriggeredRegister VDD VSS CLK D Q
parameters wp2=2.33u wn2=1.5u ln2=600n lp2=600n mult2=1
    NEGLATCH (VDD VSS CLK D inBetween) TeamXORNegativeLatch wp1=wp2 wn1=wn2 lp1=lp2 ln1=ln2 mult1=mult2
    POSLATCH (VDD VSS CLK inBetween Q) TeamXORPositiveLatch wp1=wp2 wn1=wn2 lp1=lp2 ln1=ln2 mult1=mult2 
ends TeamXORPositiveEdgeTriggeredRegister
// End of subcircuit definition.




//////////////////////////////////////////////////////////////////////////////
// 16 bit Positive Edge Triggered Register
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR16bPETR
subckt TeamXORPETR VDD VSS CLK in15 in14 in13 in12 in11 in10 in9 in8 in7 in6 in5 in4 in3 in2 in1 in0 out15 out14 ou13 \
    out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0
parameters wp3=2.33u wn3=1.5u ln3=600n lp3=600n mult3=1
    PETR15 (VDD VSS CLK in15 out15) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR14 (VDD VSS CLK in14 out14) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR13 (VDD VSS CLK in13 out13) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR12 (VDD VSS CLK in12 out12)TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR11 (VDD VSS CLK in11 out11) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR10 (VDD VSS CLK in10 out10) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR9 (VDD VSS CLK in9 out9) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR8 (VDD VSS CLK in8 out8) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR7 (VDD VSS CLK in7 out7) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR6 (VDD VSS CLK in6 out6) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR5 (VDD VSS CLK in5 out5) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR4 (VDD VSS CLK in4 out4) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR3 (VDD VSS CLK in3 out3) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR2 (VDD VSS CLK in2 out2) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR1 (VDD VSS CLK in1 out1) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
    PETR0 (VDD VSS CLK in0 out0) TeamXORPositiveEdgeTriggeredRegister wp2=wp3 wn2=wn3 lp2=lp3 ln2=ln3 mult2=mult3
ends TeamXORPETR
// End of subcircuit defintion.



//////////////////////////////////////////////////////////////////////////////
// 16 bit Pass
//////////////////////////////////////////////////////////////////////////////

// Cell Name:TeamXOR16bPass
subckt TeamXOR16bPass VDD VSS in15 in14 in13 in12 in11 in10 in9 in8 in7 in6 in5 in4 in3 in2 in1 in0 \
    out15 out14 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n alphafirst0=1 alphasecond0=1
    IPass15 (VDD VSS in15 out15) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass14 (VDD VSS in14 out14) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass13 (VDD VSS in13 out13) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass12 (VDD VSS in12 out12) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass11 (VDD VSS in11 out11) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass10 (VDD VSS in10 out10) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass9 (VDD VSS in9 out9) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass8 (VDD VSS in8 out8) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass7 (VDD VSS in7 out7) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass6 (VDD VSS in6 out6) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass5 (VDD VSS in5 out5) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass4 (VDD VSS in4 out4) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass3 (VDD VSS in3 out3) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass2 (VDD VSS in2 out2) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass1 (VDD VSS in1 out1) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
    IPass0 (VDD VSS in0 out0) TeamXORBuffer wp0=3u wn0=1.5u alphafirst=alphafirst0 alphasecond=alphasecond0
ends TeamXOR16bPass
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 8 to 1 MUX
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXOR8to1MUX
// An 8 to 1 MUX using 7 2 to 1 MUXes. It implements a pyramid style MUX, 4 - 2 - 1. The signal between
// each stage of MUXes includes a buffer. mult1 in the parameters is the multiplier for the MUXes.
// mult2 in the parameters line is the multiplier for the first inverter of the buffer. mult3 in the
// parameters line is the multiplier for the second inverter of the buffer.
// alpha0 corresponds to the alpha of the first inverter of the buffer stage between MUXes 4 and 2.
// alpha1 corresponds to the alpha of the second inverter of the buffer stage between MUXes 4 and 2.
// alpha2 corresponds to the alpha of the first inverter of the buffer stage between MUXes 2 and 1.
// alpha3 corresponds to the alpha of the second inverter of the buffer stage between MUXes 2 and 1.
// alphax allows for tapered buffering to the subsequent MUX, if needed.

subckt TeamXOR8to1MUX VDD VSS in0 in1 in2 in3 in4 in5 in6 in7 Select0 Select1 Select2 out
parameters wp1=2.33u wn1=1.5u ln1=600n lp1=600n mult1=1 alpha0=1 alpha1=1 alpha2=1 alpha3=1 mult2=1 mult3=1

// Left MUXes
MUX01 (VDD VSS in0 in1 Select0 outA) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1
MUX23 (VDD VSS in2 in3 Select0 outB) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1
MUX45 (VDD VSS in4 in5 Select0 outC) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1
MUX67 (VDD VSS in6 in7 Select0 outD) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1

// Buffer stage for left MUXes
B0 (VDD VSS outA inA) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 multfirst=mult2 alphafirst=alpha0 multsecond=mult3 alphasecond=alpha1 
B1 (VDD VSS outB inB) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 multfirst=mult2 alphafirst=alpha0 multsecond=mult3 alphasecond=alpha1 
B2 (VDD VSS outC inC) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 multfirst=mult2 alphafirst=alpha0 multsecond=mult3 alphasecond=alpha1 
B3 (VDD VSS outD inD) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 multfirst=mult2 alphafirst=alpha0 multsecond=mult3 alphasecond=alpha1 

// Middle MUXes
MUX0123 (VDD VSS inA inB Select1 outE) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1
MUX4567 (VDD VSS inC inD Select1 outF) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1

// Buffer stage for middle MUXes
B4 (VDD VSS outE inE) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 multfirst=mult2 alphafirst=alpha2 multsecond=mult3 alphasecond=alpha3 
B5 (VDD VSS outF inF) TeamXORBuffer wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 multfirst=mult2 alphafirst=alpha2 multsecond=mult3 alphasecond=alpha3 

// Right MUX
MUXFinal (VDD VSS inE inF Select2 out) TeamXOR2to1MUX wp0=wp1 wn0=wn1 lp0=lp1 ln0=ln1 mult0=mult1

ends TeamXOR8to1MUX
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// 16 bit Adder/Subtractor
//////////////////////////////////////////////////////////////////////////////

//Cell Name: TeamXOR16BitAdderSubtractor
// A 16 bit adder/subtractor using mirror adder topology.  Contains sizing parameters.
// Also contains individual sizing of mirror adders for logical effort.
subckt TeamXOR16BitAdderSubtractor VDD VSS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 \
A5 A4 A3 A2 A1 A0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Subtract \
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Cout15

parameters wpadder=2.33u wnadder=1.5u lnadder=600n lpadder=600n multadder=1 alpha0=1 alpha1=1 \
alpha2=1 alpha3=1 alpha4=1 alpha5=1 alpha6=1 alpha7=1 alpha8=1 alpha9=1 alpha10=1 \
alpha11=1 alpha12=1 alpha13=1 alpha14=1 alpha15=1


InvforCin0 (VDD 0 Subtract SubtractBar) TeamXORInverter wp=wpadder wn=wnadder ln=lnadder lp=lpadder mult=multadder

//Mux to select 0(=subtract) or 1(=add) for first Carryin
MUXCin0 (VDD 0 VDD SubtractBar Subtract Cin0) TeamXOR2to1MUX wp0=wpadder wn0=wnadder ln0=lnadder lp0=lpadder mult0=multadder

Bit0 (VDD 0 A0 B0 Cin0 Subtract S0 Coutb0) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha0 multeven=multadder

Bit1 (VDD 0 A1 B1 Coutb0 Subtract S1 Cout1) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha1 multodd=multadder

Bit2 (VDD 0 A2 B2 Cout1 Subtract S2 Coutb2) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha2 multeven=multadder

Bit3 (VDD 0 A3 B3 Coutb2 Subtract S3 Cout3) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha3 multodd=multadder

Bit4 (VDD 0 A4 B4 Cout3 Subtract S4 Coutb4) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha4 multeven=multadder

Bit5 (VDD 0 A5 B5 Coutb4 Subtract S5 Cout5) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha5 multodd=multadder

Bit6 (VDD 0 A6 B6 Cout5 Subtract S6 Coutb6) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha6 multeven=multadder

Bit7 (VDD 0 A7 B7 Coutb6 Subtract S7 Cout7) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha7 multodd=multadder

Bit8 (VDD 0 A8 B8 Cout7 Subtract S8 Coutb8) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha8 multeven=multadder

Bit9 (VDD 0 A9 B9 Coutb8 Subtract S9 Cout9) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha9 multodd=multadder

Bit10 (VDD 0 A10 B10 Cout9 Subtract S10 Coutb10) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha10 multeven=multadder

Bit11 (VDD 0 A11 B11 Coutb10 Subtract S11 Cout11) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha11 multodd=multadder

Bit12 (VDD 0 A12 B12 Cout11 Subtract S12 Coutb12) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha12 multeven=multadder

Bit13 (VDD 0 A13 B13 Coutb12 Subtract S13 Cout13) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha13 multodd=multadder

Bit14 (VDD 0 A14 B2 Cout13 Subtract S14 Coutb14) TeamXORevenbit wpeven=wpadder wneven=wnadder \
lneven=lpadder lpeven=lpadder alphaeven=alpha14 multeven=multadder

Bit15 (VDD 0 A15 B15 Coutb14 Subtract S15 Cout15) TeamXORoddbit wpodd=wpadder wnodd=wnadder \
lnodd=lpadder lpodd=lpadder alphaodd=alpha15 multodd=multadder
ends TeamXOR16BitAdderSubtractor
// End of subcircuit definition.



//////////////////////////////////////////////////////////////////////////////
// Even Bit Addition in 16 bit Adder
//////////////////////////////////////////////////////////////////////////////

// Cell name:  TeamXORevenbit
// Even bit addition
subckt TeamXORevenbit VDD VSS A B Cin Subtract S Coutb
parameters wpeven=2.33u wneven=1.5u lneven=600n lpeven=600n alphaeven=1 multeven=1
    InverterforBinput (VDD VSS B Bbar) TeamXORInverter wp=wpeven wn=wneven ln=lneven lp=lpeven alpha=alphaeven mult=multeven
    MUXforBinput (VDD VSS Bbar B Subtract inB) TeamXOR2to1MUX wp0=wpeven wn0=wneven ln0=lneven lp0=lpeven mult0=multeven alpha0=alphaeven
    MirrorAdder (VDD VSS A inB Cin Sb Coutb) TeamXORMirrorAdder wp=wpeven wn=wneven ln=lneven lp=lpeven mult=multeven alpha=alphaeven
    SumInverter (VDD VSS Sb S) TeamXORInverter wp=wpeven wn=wneven ln=lneven lp=lpeven alpha=alphaeven mult=multeven
ends TeamXORevenbit
// End of Subcircuit Definition


//////////////////////////////////////////////////////////////////////////////
// Odd Bit Addition in 16 bit Adder
//////////////////////////////////////////////////////////////////////////////

// Cell name:  TeamXORoddbit
// Odd bit addition
subckt TeamXORoddbit VDD VSS A B Cinb Subtract S Cout
parameters wpodd=2.33u wnodd=1.5u lnodd=600n lpodd=600n alphaodd=1 multodd=1
    InverterforAinput (VDD VSS A Abar) TeamXORInverter wp=wpodd wn=wnodd ln=lnodd lp=lpodd alpha=alphaodd mult=multodd
    InverterforBinput (VDD VSS B Bbar) TeamXORInverter wp=wpodd wn=wnodd ln=lnodd lp=lpodd alpha=alphaodd mult=multodd
    MUXforBinput (VDD VSS B Bbar Subtract inBbar) TeamXOR2to1MUX wp0=wpodd wn0=wnodd ln0=lnodd lp0=lpodd mult0=multodd alpha0=alphaodd
    MirrorAdder (VDD VSS Abar inBbar Cinb S Cout) TeamXORMirrorAdder wp=wpodd wn=wnodd ln=lnodd lp=lpodd mult=multodd alpha=alphaodd
ends TeamXORoddbit
// End of Subcircuit Definition



//////////////////////////////////////////////////////////////////////////////
// Mirror Adder
//////////////////////////////////////////////////////////////////////////////

// Cell name: TeamXORMirrorAdder
// A Full Adder with a Mirror Adder topology.  Contains sizing parameters and parameterized AD, AS, PD, PS
// Also contains sizing parameter alpha for the Cin tranistors for minimizing worst-case delay
subckt TeamXORMirrorAdder VDD VSS A B Cin Sb Coutb
parameters wp=2.33u wn=1.5u ln=600n lp=600n alpha=1 mult=1

P11 (node9 B VDD VDD) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp ps=3u+3*wp pd=3u+3*wp \
        m=mult 
P10 (node8 A node9 VDD) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp ps=3u+3*wp pd=3u+3*wp m=mult \
        
P9 (Sb Cin node8 VDD) ami06P w=alpha*3*wp l=lp as=1.5u*alpha*3*wp ad=1.5u*alpha*3*wp ps=3u+alpha*3*wp pd=3u+alpha*3*wp \
        m=mult 
P8 (node5 A VDD VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp m=mult \
        
P7 (node5 B VDD VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp m=mult \
        
P6 (node5 Cin VDD VDD) ami06P w=alpha*2*wp l=lp as=1.5u*alpha*2*wp ad=1.5u*alpha*2*wp ps=3u+alpha*2*wp pd=3u+alpha*2*wp \
        m=mult 
P5 (Sb Coutb node5 VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp \
        m=mult 
P4 (Coutb Cin node0 VDD) ami06P w=alpha*6*wp l=lp as=1.5u*alpha*6*wp ad=1.5u*alpha*6*wp ps=3u+alpha*6*wp pd=3u+alpha*6*wp \
        m=mult 
P3 (Coutb A node3 VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp \
        m=mult 
P2 (node3 B VDD VDD) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp pd=3u+2*wp m=mult
        
P1 (node0 B VDD VDD) ami06P w=6*wp l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+6*wp pd=3u+6*wp m=mult
        
P0 (node0 A VDD VDD) ami06P w=6*wp l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+6*wp pd=3u+6*wp m=mult
        
N11 (node6 B VSS VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=1.5u+3*wn \
	pd=1.5u+3*wn m=mult 
N10 (node7 A node6 VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=1.5u+3*wn pd=1.5u+3*wn \
        m=mult 
N9 (Sb Cin node7 VSS) ami06N w=alpha*3*wn l=ln as=1.5u*alpha*3*wn ad=1.5u*alpha*3*wn ps=1.5u+alpha*3*wn \
        pd=1.5u+alpha*3*wn m=mult 
N8 (node4 A VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=1.5u+2*wn \
        pd=1.5u+2*wn m=mult 
N7 (node4 B VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=1.5u+2*wn \
        pd=1.5u+2*wn m=mult 
N6 (node4 Cin VSS VSS) ami06N w=alpha*2*wn l=ln as=1.5u*alpha*2*wn ad=1.5u*alpha*2*wn ps=1.5u+alpha*2*wn \
        pd=1.5u+alpha*2*wn m=mult 
N5 (Sb Coutb node4 VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=1.5u+2*wn \
        pd=1.5u+2*wn m=mult 
N4 (Coutb A node2 VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=1.5u+2*wn \
        pd=1.5u+2*wn m=mult 
N3 (node2 B VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=1.5u+2*wn pd=1.5u+2*wn \
        m=mult 
N2 (Coutb Cin node1 VSS) ami06N w=alpha*6*wn l=ln as=1.5u*alpha*6*wn ad=1.5u*alpha*6*wn ps=1.5u+alpha*6*wn \
        pd=1.5u+alpha*6*wn m=mult 
N1 (node1 B VSS VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=1.5u+6*wn pd=1.5u+6*wn \
        m=mult 
N0 (node1 A VSS VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=1.5u+6*wn pd=1.5u+6*wn \
        m=mult     
ends TeamXORMirrorAdder
// End of Subcircuit Definition

//////////////////////////////////////////////////////////////////////////////
// Mirror Adder
//////////////////////////////////////////////////////////////////////////////


// TeamXOR ALU
// Control Signals:
// 000 - Multiply A7...A0 by B7...B0
// 001 - Pass A15...A0
// 010 - AND A15...A0 with B15...B0
// 011 - OR A15...A0 with B15...B0
// 100 - Add A15...A0 to B15...B0
// 101 - Subtract A15...A0 by B15...B0
// 110 - Shift A15...A0 by: 1 when B1B0=00, by 2 when B1B0=01, by 3 when B1B0=10, by 4 when B1B0=11
// 111 - No Operation.  Output of ALU remains the same

subckt TeamXORALU VDD VSS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 \
S2 S1 S0 Out15 Out14 Out13 Out12 Out11 Out10 Out9 Out8 Out7 Out6 Out5 Out4 Out3 Out2 Out1 Out0 CarryOut


/////////////////////////////////////////////////////////////////////////////////
//Arbitrary Function - Control Line = 000 - Set it to Ground for Testing
/////////////////////////////////////////////////////////////////////////////////

VAF15 (Line0b15 0) vsource type=dc dc=0
VAF14 (Line0b14 0) vsource type=dc dc=0
VAF13 (Line0b13 0) vsource type=dc dc=0
VAF12 (Line0b12 0) vsource type=dc dc=0
VAF11 (Line0b11 0) vsource type=dc dc=0
VAF10 (Line0b10 0) vsource type=dc dc=0
VAF9 (Line0b9 0) vsource type=dc dc=0
VAF8 (Line0b8 0) vsource type=dc dc=0
VAF7 (Line0b7 0) vsource type=dc dc=0
VAF6 (Line0b6 0) vsource type=dc dc=0
VAF5 (Line0b5 0) vsource type=dc dc=0
VAF4 (Line0b4 0) vsource type=dc dc=0
VAF3 (Line0b3 0) vsource type=dc dc=0
VAF2 (Line0b2 0) vsource type=dc dc=0
VAF1 (Line0b1 0) vsource type=dc dc=0
VAF0 (Line0b0 0) vsource type=dc dc=0

/////////////////////////////////////////////////////////////////////////////////
//Pass A - Control Line = 001
/////////////////////////////////////////////////////////////////////////////////

PASSA16b (VDD VSS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Line1b15 Line1b14 \
		Line1b13 Line1b12 Line1b11 Line1b10 Line1b9 Line1b8 Line1b7 Line1b6 Line1b5 \
		Line1b4 Line1b3 Line1b2 Line1b1 Line1b0) TeamXOR16bPass

/////////////////////////////////////////////////////////////////////////////////
//AND - Control Line = 010
/////////////////////////////////////////////////////////////////////////////////

AND16b (VDD VSS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 \
	B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Line2b15 Line2b14 Line2b13 \
	Line2b12 Line2b11 Line2b10 Line2b9 Line2b8 Line2b7 Line2b6 \
	Line2b5 Line2b4 Line2b3 Line2b2 Line2b1 Line2b0) TeamXOR16b2inAND

/////////////////////////////////////////////////////////////////////////////////
//OR - Control Line = 011
/////////////////////////////////////////////////////////////////////////////////

OR16b (VDD VSS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 \
	 Line3b15 Line3b14 Line3b13 Line3b12 Line3b11 Line3b10 Line3b9 Line3b8 Line3b7 Line3b6 Line3b5 Line3b4 Line3b3 \
	 Line3b2 Line3b1 Line3b0) TeamXOR16b2inOR

/////////////////////////////////////////////////////////////////////////////////
//Add/Subtract - Control Line = 100/101
/////////////////////////////////////////////////////////////////////////////////

ADDSUB16b (VDD VSS A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Subtract \
	Line45b15 Line45b14 Line45b13 Line45b12 Line45b11 Line45b10 Line45b9 Line45b8 Line45b7 Line45b6 Line45b5 Line45b4 Line45b3 Line45b2 Line45b1 Line45b0 CarryOut) TeamXOR16BitAdderSubtractor

/////////////////////////////////////////////////////////////////////////////////
//Shift - Control Line = 110
/////////////////////////////////////////////////////////////////////////////////

Shift16b (VDD VSS B1 B0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Line6b15 Line6b14 Line6b13 \
	Line6b12 Line6b11 Line6b10 Line6b9 Line6b8 Line6b7 Line6b6 Line6b5 Line6b4 Line6b3 Line6b2 Line6b1 Line6b0) TeamXOR16bShifter

/////////////////////////////////////////////////////////////////////////////////
//NOP - Control Line = 111
/////////////////////////////////////////////////////////////////////////////////

NOP16b (VDD VSS Out15 Out14 Out13 Out12 Out11 Out10 Out9 Out8 Out7 Out6 Out5 Out4 Out3 Out2 Out1 Out0 Line7b15 Line7b14 \
		Line7b13 Line7b12 Line7b11 Line7b10 Line7b9 Line7b8 Line7b7 Line7b6 Line7b5 \
		Line7b4 Line7b3 Line7b2 Line7b1 Line7b0) TeamXOR16bPass
		
/////////////////////////////////////////////////////////////////////////////////
//8 to 1 MUX Connecting All Functions - 16 Bits
/////////////////////////////////////////////////////////////////////////////////

8to1MUXb15 (VDD VSS Line0b15 Line1b15 Line2b15 Line3b15 Line45b15 Line45b15 Line6b15 Line7b15 S0 S1 S2 Out15) TeamXOR8to1MUX
8to1MUXb14 (VDD VSS Line0b14 Line1b14 Line2b14 Line3b14 Line45b14 Line45b14 Line6b14 Line7b14 S0 S1 S2 Out14) TeamXOR8to1MUX
8to1MUXb13 (VDD VSS Line0b13 Line1b13 Line2b13 Line3b13 Line45b13 Line45b13 Line6b13 Line7b13 S0 S1 S2 Out13) TeamXOR8to1MUX
8to1MUXb12 (VDD VSS Line0b12 Line1b12 Line2b12 Line3b12 Line45b12 Line45b12 Line6b12 Line7b12 S0 S1 S2 Out12) TeamXOR8to1MUX
8to1MUXb11 (VDD VSS Line0b11 Line1b11 Line2b11 Line3b11 Line45b11 Line45b11 Line6b11 Line7b11 S0 S1 S2 Out11) TeamXOR8to1MUX
8to1MUXb10 (VDD VSS Line0b10 Line1b10 Line2b10 Line3b10 Line45b10 Line45b10 Line6b10 Line7b10 S0 S1 S2 Out10) TeamXOR8to1MUX
8to1MUXb9 (VDD VSS Line0b9 Line1b9 Line2b9 Line3b9 Line45b9 Line45b9 Line6b9 Line7b9 S0 S1 S2 Out9) TeamXOR8to1MUX
8to1MUXb8 (VDD VSS Line0b8 Line1b8 Line2b8 Line3b8 Line45b8 Line45b8 Line6b8 Line7b8 S0 S1 S2 Out8) TeamXOR8to1MUX
8to1MUXb7 (VDD VSS Line0b7 Line1b7 Line2b7 Line3b7 Line45b7 Line45b7 Line6b7 Line7b7 S0 S1 S2 Out7) TeamXOR8to1MUX
8to1MUXb6 (VDD VSS Line0b6 Line1b6 Line2b6 Line3b6 Line45b6 Line45b6 Line6b6 Line7b6 S0 S1 S2 Out6) TeamXOR8to1MUX
8to1MUXb5 (VDD VSS Line0b5 Line1b5 Line2b5 Line3b5 Line45b5 Line45b5 Line6b5 Line7b5 S0 S1 S2 Out5) TeamXOR8to1MUX
8to1MUXb4 (VDD VSS Line0b4 Line1b4 Line2b4 Line3b4 Line45b4 Line45b4 Line6b4 Line7b4 S0 S1 S2 Out4) TeamXOR8to1MUX
8to1MUXb3 (VDD VSS Line0b3 Line1b3 Line2b3 Line3b3 Line45b3 Line45b3 Line6b3 Line7b3 S0 S1 S2 Out3) TeamXOR8to1MUX
8to1MUXb2 (VDD VSS Line0b2 Line1b2 Line2b2 Line3b2 Line45b2 Line45b2 Line6b2 Line7b2 S0 S1 S2 Out2) TeamXOR8to1MUX
8to1MUXb1 (VDD VSS Line0b1 Line1b1 Line2b1 Line3b1 Line45b1 Line45b1 Line6b1 Line7b1 S0 S1 S2 Out1) TeamXOR8to1MUX
8to1MUXb0 (VDD VSS Line0b0 Line1b0 Line2b0 Line3b0 Line45b0 Line45b0 Line6b0 Line7b0 S0 S1 S2 Out0) TeamXOR8to1MUX


ends TeamXORALU
// End of subcircuit definition. 

